ALU_Control_Unit Project Status | |||
Project File: | Processor_Organwsi.xise | Parser Errors: | X 1 Error |
Module Name: | ALU_Control_Unit | Implementation State: | New |
Target Device: | xc3s400-4fg320 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Πεμ 20. Απρ 22:31:10 2023 |