Partial Reconfiguration Cost Calculator (PRCC)

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We are glad this work helps pursuing research in various domains exploring the use of PR technology.

last update: Oct 19, 2019 - new significant entries appear with magenta color
©2010 Kyprianos Papadimitriou
contact:  kpapadimitriou  isc.tuc.gr

This formula calculates the time needed for partial reconfiguration using the internal reconfiguration port, i.e. ICAP, when controlled by the on-chip processor. It was derived based on experiments conducted on an evaluation platform. It targets Xilinx Virtex FPGAs and provides a fair estimation for different system setups using PowerPC as the reconfiguration controller. It can be used for other processors such as the Microblaze but with less accuracy. Different ways to control reconfiguration exist and certainly the incorporation of a dedicated controller offers a faster solution as compared to the on-chip processor (in WRC 2014 paper we reached a throughput of 488 MB/s). There are applications in which the reconfiguration needs to be controlled by the processor, or cases in which the researcher needs to be aware of the reconfiguration time without putting the effort or devoting resources to implement a dedicated controller. PRCC aims at supporting researchers in assessing their system and taking decisions at an early development stage prior to entering the PR design flow.

INPUT

OUTPUT

Instructions to use the PRCC

• External memory : type of memory storing the partial bitstreams; two options are available, Compact Flash (CF) and DDR
• Memory bus clock rate (MHz) : clock rate of the bus connecting the external memory to the FPGA
• Memory interface width (bits) : width of the interface with external memory
• Internal bus : type of the on-chip bus that connects the on-chip processor with the reconfigurable fabric; two options are available, OPB and PLB
• Processor cache : choose whether the processor's cache is enabled
• Device : targetted devices belong to Xilinx Virtex family. The selection affects the following four characteristics (you can watch that the fields lying beneatch the "Device" field are changing values once a different device is selected).
• Partial bitstream size (KB): enter the size of the bitstream in KBytes

Experimental framework and theory used to extract the formula

• K. Papadimitriou, A. Anyfantis, A. Dollas, "Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead", IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 335-336, Napa CA, USA, April 2007.
• K. Papadimitriou, A. Anyfantis, A. Dollas, "An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems", IEEE Transactions on Instrumentation and Measurement (TIM), vol. 59, no. 6, pp. 1642-1651, June 2010.
• K. Papadimitriou, A. Dollas, S. Hauck, "Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4, no. 4, December 2011.

Research areas that can benefit from using the formula

• Published works on different application domains that cited or used PRCC for evaluating their systems:
  • N. Alachiotis, A. Stamatakis, "A Generic and Versatile Architecture for Inference of Evolutionary Trees under Maximum Likelihood", Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers, November 2010.
  • A. H. Gholamipour, K. Papadimitriou, F. Kurdahi, A. Dollas, A. Eltawil, "Area, Reconfiguration Delay and Reliability Trade-Offs in Designing Reliable Multi-Mode FIR Filters", IEEE International Design and Test Workshop (IDT), in conjunction with the IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 82-87, Beirut, Lebanon, December 2011.
  • M. E. Wenxue Gao, "Active Buffer Development in CBM Experiment", Doctoral dissertation, Heidelberg University, March 2012.
  • N. Alachiotis, "Algorithms and Computer Architectures for Evolutionary Bioinformatics", Doctoral dissertation, Technical University of Munich, October 2012.
  • R. Cattaneo, C. Pilato, G. C. Durelli, M. D. Santambrogio, D. Sciuto, "SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs", International Symposium on Rapid System Prototyping (RSP), Montreal, Canada, October 2013.
  • R. Cattaneo, "On the Role of Polyhedral Analysis in High Performance Reconfigurable Hardware Based Computing Systems", Doctoral dissertation, Politecnico di Milano, 2015.
  • Mai-Thanh Tran, M. Gautier, E. Casseau, "On the FPGA-based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study", EAI International Conference on Cognitive Radio Oriented Wireless Networks (CROWNCOM), Grenoble, France, May 2016.
  • Mai-Thanh Tran, "Towards hardware synthesis of a flexible radio from a high-level language", Doctoral dissertation, Computer Science, Université de Rennes 1, 2018.
  • J. Romoth, "FPGA-Cluster", Doctoral dissertation, Bielefeld University, 2018.

• Scheduling tasks in PR systems where the embedded processor loads modules to the reconfigurable fabric for acceleration:
  • S. Hauck, "Configuration Prefetch for Single Context Reconfigurable Coprocessors", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 65-74, Monterey CA, USA, February 1998.
  • S. Banerjee, E. Bozorgzadeh, N. Dutt, "Considering Run-time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures", IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 273-274, Napa CA, USA, April 2005.
  • K. Papadimitriou, A. Dollas, "A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems", IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 307-308, Napa CA, USA, April 2006.
  • K. Papadimitriou, A. Dollas, "Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors", IEEE International Conference on Field Programmable Logic and Aplications (FPL), pp. 901-904, Madrid, Spain, August 2006.
  • M. D. Santambrogio, M. Redaelli, M. Maggioni, "Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse", ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 21-26, Boston Area MA, USA, 2009.
  • J. E. Sim, W. Wong, G. Walla, T. Ziermann, J. Teich, "Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems", IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 179-182, Charlotte NC, USA, May 2010.
  • Y. Lu, T. Marconi, K.L.M. Bertels, G. N. Gaydadjiev, "A Communication Aware Online Task Scheduling Algorithm for FPGA-based Partially Reconfigurable Systems", IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 65-68, Charlotte NC, USA, May 2010.
  • G. Charitopoulos, I. Koidis, K. Papadimitriou, D. Pnevmatikatos, "Hardware Task Scheduling for Partially Reconfigurable FPGAs", International Symposium on Applied Reconfigurable Computing (ARC), pp. 487-498, Bochum, Germany, April 2015.

• Switching between the tasks of an application or between entire applications:
  • C. Kachris, S. Vassiliadis, "Performance Evaluation of an Adaptive FPGA for Network Applications", IEEE International Workshop on Rapid System Prototyping (RSP), pp. 54-62, Chania, Greece, June 2006.
  • A. H. Gholamipour, H. Eslami, A. Eltawil, F. Kurdahi, "Size-Reconfiguration Delay Tradeoffs for a Class of DSP Block in Multi-mode Communication Systems", IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 71-78, Napa CA, USA, April 2009.
  • C. Effraimidis, K. Papadimitriou, A. Dollas, I. Papaefstathiou, "A Self-Reconfiguring Architecture Supporting Multiple Objective Functions in Genetic Algorithms", IEEE International Conference on Field Programmable Logic and Aplications (FPL), pp. 453-456, Prague, Czech Republic, August 2009.
  • S. Khan, K. Papadimitriou, G. Buttazzo, K. Kalaitzakis, "A Reconfigurable PID Controller", International Symposium on Applied Reconfigurable Computing (ARC), pp. 392-403, Santorini, Greece, May 2018.

• Fault recovery methods in systems using partial reconfiguration for correction from faults. In such systems the period the system remains unreliable, i.e. an error cannot be detected or correction actions cannot be immediately taken, depends on the reconfiguration delay:
  • A. Ilias, K. Papadimitriou, A. Dollas, "Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-based FPGAs", IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 73-76, Charlotte NC, USA, May 2010.
  • M. Vavouras, C. Bouganis, "Area-driven Partial Reconfiguration for SEU Mitigation on SRAM-based FPGAs", IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6, Cancun, Mexico, December 2016.