Kyprianos Papadimitriou Ph.D

Quick-view profile google scholar and Laboratory teaching [gr] [en] Visiting professor 2018-19 [gr] [en] Research collab. UW 2009, FORTH 2011-14, HMU 2014-17 In top-4 cited articles of ACM TRETS journal Best paper nominee in VLSI-SoC 2013 FPGAs in desktops - position paper in ReCoSoC 2012 Ph.D in Jan 2012 Partial Reconfiguration Cost Calculator ©2010 KP US patent on pattern matching and start-up 2003-05 Bluetooth v1.0 chip when I was with Atmel 1998-99 email: kpapadimitriou  isc.tuc.gr ,  k.papadimitriou  nup.ac.cy tel: +30 2821037219 Chania, Crete, 73100, Greece office: Sciences' buidling, 137.B.69

• In ARC 2020 and ReConFig 2019 program committees.
• Reviewed for IEEE Access; IET Electronics Letters; ACM TRETS; ARC; ReCoSoC; ReConFig.
• Visiting professor at Neapolis University Pafos, Department of Computer Science. WINNER 'TOP-100. ACHIEVEMENTS-2019' in science & education.
• An article in ACM TRETS journal reached a place amongst its top-3 cited articles according to google scholar; in its top-4 according to ACM digital library - sorted by "Cited".
• Book chapter "Chip-Level Communication Services" in Distributed Real-Time Architecture for Mixed-Criticality-Systems, CRC Press, Aug 2018.
  
• Slides of paper "A Reconfigurable PID Controller", ARC 2018; it is on fast feedback control loop. A related article was published in the local press.
  
• Slides of paper "Address Interleaving for Low-Cost NoCs", ReCoSoC 2016 (If interested I suggest to download and view them in presentation mode because they contain animation).
  
• In ARC 2018 I initiated a special session focusing on the industrial real-time domain.

• 2 papers on Partial Reconfiguration of FPGAs, one in Integration, the VLSI Journal 2017 and one in ARC 2018.
• 3 conference papers on Mixed-Criticality Systems and On-Chip Networks, in IEEE ASAP 2016 and ReCoSoC 2016.
• Poster "Dynamic Frequency Scaling and Load Balancing in NoC-based MPSoCs for Mixed-Criticality Applications" in HiPEAC 2016.
• In the top-5 cited articles of ACM TRETS journal according to google scholar; ACM TRETS started publishing in 2008.
• Since 2014, 2 EU projects: TRESCCA and DREAMS.
• Invited talk in ARC 2014.
• 2013-16 and 2016-19, member of the Representative Board of Electronic and Computer Engineers, Central Delegation of the Technical Chamber of Greece. It consists of 5 Electronic and Computer Engineers elected across Greece.

• Partial reconfiguration (PR) of FPGAs; try PRCC to calculate the PR time [website has been updated]
• Runtime systems
• Reliability in reconfigurable hardware
• Task scheduling in partially reconfigurable FPGAs
• Application acceleration in reconfigurable hardware
• Radio Frequency Identification (RFID)
• Network-on-Chip
• Control systems

• Technical University of Crete, Electronic and Computer Engineering, 2012 Ph.D, 2003 M.Sc.Eng, 1997 B.Eng

• Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model, ACM TRETS 2011
  
• Acceleration of Computationally-Intensive Kernels in the Reconfigurable Era, ReCoSoC 2012
  
• Hardware Task Scheduling for Partially Reconfigurable FPGAs, ARC 2015
  
• Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-based FPGAs, IEEE FCCM 2010
  
• Security Enhancements for Building Saturation-free, Low-power NoC-based MPSoCs, IEEE CNS 2015
  
• Address Interleaving for Low-cost NoCs, ReCoSoC 2016
  

• Jan 2014 - June 2017, Hellenic Mediterranean University (former Technological Educational Institute of Crete, Heraklion GR)
  Research collaborator
  • Secure and real-time Networks-on-Chip


• Sep 2011 - Nov 2014, Foundation for Research & Technology - Hellas (Heraklion GR)
  Research associate, project FASTER
  • Control reconfiguration in FPGA systems


• Nov 2012 - July 2013, Technical University of Crete (Chania GR)
  Senior technical staff, project on RFID technology for maritime transportations (MERIT)
  • System structure
  • Study of RFID technologies
  • Integration with existing infrastructure of shipping companies


• June 2003 - Jan 2012, Technical University of Crete (Chania GR),
  Ph.D research
  Studied novel ways to use partial and dynamic reconfiguration of FPGAs in different research fields
  • Designed a hybrid system coupling software and reconfigurable hardware for handling soft faults, which incurs lower resource overhead over Triple Modular Redundancy (TMR)
  • Shaped a formula to calculate the reconfiguration overhead for different setups based on experimental data and theoretical analysis (PRCC)
  • Modeled task scheduling in PR FPGAs using task graphs
  • Experimented with the PR design flow on Virtex-II Pro and Virtex-5 FPGAs



Feb 2009 - Apr 2009, University of Washington (Seattle US), Predoctoral scholar Studied domains that can benefit from partial reconfiguration technology; studied commercial reconfigurable coarse-grained architectures Oct 2003 - May 2005, Independent development program (Chania GR) Principal investigator for the commercialization of a research result through spin-off In-more-Tech Supervised the development and validation of the 3rd generation input device for handicapped people Undertook presentations and talks in exhibitions Involved in writing the patent US Patent 7,583,819

• Mar 2002 - Dec 2007, Technical University of Crete (Chania GR)
  Coordinated a program for the encouragement of entrepreneurship in Internet-based businesses of small-medium enterprises through educational support (go-online)
  • Administrated the educations carried out by 64 educators in a total of 1250 small-medium enterprises in the prefectures of Chania and Rethymnon, Crete
  • Identified, selected and prepared the educators
  • Financial management (€ 524,000)


• Jan 2001 - June 2001, Technical University of Crete (Chania GR),
  M.S research
  • Assisted the validation of an active network platform by writing testbench code and testing the hardware with a logic analyzer
  • Developed the 2nd generation input device for handicapped people


• Mar 2000 - Dec 2000, Technical University of Crete (Chania GR),
  M.S research
  Prototyped a system using software (C & Visual Basic), designed the system in Verilog HDL, developed microprocessor code in Assembly, constructed several printed circuit boards
  • Designed and implemented an embedded low cost input device coupling an FPGA with a microcontroller for processing acceleration signals to assist handicapped people in controlling electronic equipment such as home appliances and wheelchairs
  • Prototyped the system processing using an application on a PC connected with an accelerometer-based and microcontroller subsystem


• Mar 1998 - July 1999, Atmel Hellas S.A. (Patras GR)
  Worked in the R&D department; designed telecommunication systems in Verilog HDL
  • Designed, developed and simulated a baseband processor for ATMEL's Single-Chip Bluetooth controller AT76C551
  • Ported the hardware design of a wireless LAN telecommunication protocol in ATMEL's FPGA design tools

Publications that appear in IEEE Conferences or Journals are subject to the ©IEEE Copyright policies. Publications that appear in ACM Conferences or Journals are subject to the ©ACM Copyright policies. IEEE and ACM own the copyright to all material published by the IEEE and ACM respectively. Personal use of this material is permitted.

Journals

1. G. Charitopoulos, I. Koidis, K. Papadimitriou, D. Pnevmatikatos
   Run-Time Management of Systems with Partially Reconfigurable FPGAs (online)
   ELSEVIER Integration, the VLSI Journal, 57, pp. 34-44, 2017. [I/F: 1.150]
   
   
2. D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Bohm, A. Brokalakis, K. Bruneel, C. Ciobanu
   T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato,
   M. D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman , E. Vansteenkiste
   FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
   ELSEVIER Journal on Microprocessors and Microsystems (MICPRO), 39(4-5), pp. 321-338, 2015. [I/F: 1.045]
   
   
3. M. D. Grammatikakis, K. Papadimitriou, P. Petrakis, A. Papagrigoriou, G. Kornaros, I. Christoforakis
   O. Tomoutzoglou, G. Tsamis, M. Coppola
   Security in MPSoCs: A NoC Firewall and an Evaluation Framework
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), special issue on Hardware Security and Trust, 34(8), pp. 1344-1357, Aug, 2015. I/F: 2.402]. also in gem5
   
   
4. K. Papadimitriou, A. Dollas, S. Hauck
   Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model
   ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4, no. 4, December 2011. [I/F: 1.409]. In top cited articles of ACM TRETS.
   
   
5. K. Papadimitriou, A. Anyfantis, A. Dollas
   An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
   IEEE Transactions on Instrumentation and Measurement (TIM), vol. 59, no. 6, pp. 1642-1651, June 2010. [I/F: 3.097]
   
   
6. K. Papadimitriou, A. Dollas, S. Sotiropoulos
   Low Cost Real-Time 2-D Motion Detection based on Reconfigurable Computing
   IEEE Transactions on Instrumentation and Measurement (TIM), vol. 55, no. 6, pp. 2234-2243, December 2006. [I/F: 3.097]
   
   
7. A. Dollas, S. Sotiropoulos, K. Papademetriou
   A 2D Motion Detection Model for Low Cost Embedded Reconfigurable I/O Devices
   IEEE Transactions on Biomedical Engineering (TBME), vol. 52, no. 8, pp. 1443-1449, August 2005. [I/F: 4.491]
   
   

Book Chapters

8. M. Grammatikakis, H. Ahmadian, M. Coppola, S. Kavvadias, A. Mouzakitis, K. Papadimitriou, A. Papagrigoriou, P. Petrakis, V. Piperaki, M. Soulié, G. Tsamis
   Chip-Level Communication Services
   Book Chapter in Distributed Real-Time Architecture for Mixed-Criticality Systems, CRC Press, 2018
   
   
9. K. Papadimitriou, S. Thomas, A. Dollas
   An FPGA-based Real-time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation
   Springer Book; peer-reviewed selected papers from the 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 168-187, 2013.
   
   

Conferences

10. S. Khan, K. Papadimitriou, G. Buttazzo, K. Kalaitzakis
    A Reconfigurable PID Controller
    International Symposium on Applied Reconfigurable Computing (ARC), Santorini, GR, May 2018.
    
    
11. P. Petrakis, M. Abuteir, M. D. Grammatikakis, K. Papadimitriou, R. Obermaisser, Z. Owda, A. Papagrigoriou, M. Soulie, M. Coppola
    On-Chip Networks for Mixed-Criticality Systems
    IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), London, UK, July 2016.
    
    
12. M. D. Grammatikakis, K. Papadimitriou, P. Petrakis, M. Coppola, M. Soulie
    Address Interleaving for Low-cost NoCs - Slides
    International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Tallinn, Estonia, June 2016.
    
    
13. G. Tsamis, S. Kavvadias, A. Papagrigoriou, M. D. Grammatikakis, K. Papadimitriou
    Efficient Bandwidth Regulation at a Memory Controller for Mixed-Criticality Applications
    International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Tallinn, Estonia, June 2016.
    
    
14. K. Papadimitriou, P. Petrakis, M. Grammatikakis, M. Coppola
    Security Enhancements for Building Saturation-free, Low-power NoC-based MPSoCs
    IEEE International Workshop on Security and Privacy in Cybermatics (SPiCy), in conjunction with the IEEE International Conference on Communications and Network Security (CNS), Florence, Italy, Sep 2015. also in gem5
    
    
15. G. Charitopoulos, D. Pnevmatikatos, M. Santambrogio, K. Papadimitriou, D. Pnevmatikatos
    A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board
    ParaFPGA: Parallel Computing with FPGAs, in conjunction with the International Conference on Parallel Computing (ParCo), Edinburgh, UK, Sep 2015.
    
    
16. G. Charitopoulos, I. Koidis, K. Papadimitriou, D. Pnevmatikatos
    Hardware Task Scheduling for Partially Reconfigurable FPGAs (extended version of HiPEAC WRC'15 paper)
    International Symposium on Applied Reconfigurable Computing (ARC), Bochum, Germany, April 2015.
    
    
17. G. Charitopoulos, I. Koidis, K. Papadimitriou, D. Pnevmatikatos
    Hardware Task Scheduling for Partially Reconfigurable FPGAs
    HiPEAC Workshop on Reconfigurable Computing (WRC), Amsterdam, Netherlands, January 2015.
    
    
18. M. D. Grammatikakis, K. Papadimitriou, P. Petrakis, A. Papagrigoriou, G. Kornaros, I. Christoforakis, M. Coppola
    Security Effectiveness and a Hardware Firewall for MPSoCs
    6th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2), in conjunction with the 16th IEEE International Conference on High Performance Computing and Communications (HPCC), Paris, France, August 2014. also in gem5
    
    
19. D. N. Pnevmatikatos, T. Becker, A. Brokalakis, G. N. Gaydadjiev, W. Luk, K. Papadimitriou,
    I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M. D. Santambrogio, D. Sciuto, D. Stroobandt
    Effective Reconfigurable Design: The FASTER Approach
    International Symposium on Applied Reconfigurable Computing (ARC), Vilamoura, Portugal, April 2014.
    
    
20. C. Vatsolakis, K. Papadimitriou, D. Pnevmatikatos
    Enabling Dynamically Reconfigurable Technologies in Mid Range Computers Through PCI Express
    HiPEAC Workshop on Reconfigurable Computing (WRC), Vienna, Austria, January 2014.
    
    
21. G. Rematska, K. Papadimitriou, A. Dollas
    A Low-Cost Embedded Real-Time 3D Stereo Matching System for Surveillance Applications
    IEEE International Symposium on Monitoring and Surveillance Research (ISMSR), in conjunction with the IEEE International Conference on Bioinformatics and Bioengineering (BIBE), Chania, Greece, November 2013.
    
    
22. S. Thomas, K. Papadimitriou, A. Dollas
    Architecture and Implementation of Real-Time 3D Stereo Vision on a Xilinx FPGA
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, October 2013. Nominated for best paper award.
    
    
23. C. B. Ciobanu, K. D. Papadimitriou, D. N. Pnevmatikatos, G. N. Gaydadjiev
    FASTER Run-Time Reconfiguration Management
    ACM 27th International Conference on Supercomputing (ICS), Oregon, US, June 2013.
    
    
24. M. D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto
    The FASTER Vision for Designing Dynamically Reconfigurable Systems (invited)
    IEEE International Conference on IC Design and Technology (ICICDT), Pavia, Italy, May 2013.
    
    
25. K. Papadimitriou, C. Pilato, D. Pnevmatikatos, M. D. Santambrogio, C. Ciobanu, T. Todman,
    T. Becker, X. Niu, T. Davidson, G. Gaydadjiev, W. Luk, D. Stroobandt
    Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration
    IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Paphos, Cyprus, December 2012.
    
    
26. K. Papadimitriou, D. Pnevmatikatos, A. Dollas, C. Koulamas, S. Aggelidakis, P. Chatzidakis, L. Vasilikiotis, M. Emmanouilidou
    Developing RFID-based Systems for Security in Marine Transportations
    Panhellenic Conference on Informatics (PCI), Athens, GR, October 2012.
    
    
27. D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou,
    I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M. D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman
    FASTER: Facilitating Analysis and Synthesis Technologes for Effective Reconfiguration
    Euromicro Conference on Digital System Design (DSD), Cesme, Izmir, Turkey, September 2012.
    
    
28. K. Papadimitriou, C. Vatsolakis, D. Pnevmatikatos
    Acceleration of Computationally-Intensive Kernels in the Reconfigurable Era (invited)
    IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK, July 2012.
    
    
29. M. D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt,
    T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G. C. Durelli, D. Sciuto
    Smart Technologies for Effective Reconfiguration: The FASTER Approach
    IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK, July 2012.
    
    
30. A. H. Gholamipour, K. Papadimitriou, F. Kurdahi, A. Dollas, A. Eltawil
    Area, Reconfiguration Delay and Reliability Trade-Offs in Designing Reliable Multi-Mode FIR Filters
    IEEE International Design and Test Workshop (IDT), in conjunction with the IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 82-87, Beirut, Lebanon, December 2011.
    
    
31. A. Ilias, K. Papadimitriou, A. Dollas
    Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-based FPGAs
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 73-76, Charlotte NC, USA, May 2010.
    
    
32. C. Effraimidis, K. Papadimitriou, A. Dollas, I. Papaefstathiou
    A Self-Reconfiguring Architecture Supporting Multiple Objective Functions in Genetic Algorithms
    IEEE International Conference on Field Programmable Logic and Aplications (FPL), pp. 453-456, Prague, Czech Republic, August 2009.
    
    
33. M. Vavouras, K. Papadimitriou, I. Papaefstathiou
    High-speed FPGA-based Implementations of a Genetic Algorithm
    IEEE International Conference on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS), pp. 9-16, Samos, Greece, July 2009.
    
    
34. M. Vavouras, K. Papadimitriou, I. Papaefstathiou
    Implementation of a Genetic Algorithm on a Virtex-II Pro FPGA
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), p. 287, Monterey CA, USA, February 2009.
    
    
35. K. Papadimitriou, A. Anyfantis, A. Dollas
    Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 335-336, Napa CA, USA, April 2007.
    
    
36. K. Papadimitriou, A. Dollas
    Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors
    IEEE International Conference on Field Programmable Logic and Aplications (FPL), pp. 901-904, Madrid, Spain, August 2006.
    
    
37. K. Papademetriou, A. Dollas
    A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 307-308, Napa CA, USA, April 2006.
    
    
38. A. Dollas, K. Papademetriou, E. Sotiriades, D. Theodoropoulos, I. Koidis, G. Vernardos
    A Case Study on Rapid Prototyping of Hardware Systems: the Effect of CAD Tool Capabilities, Design Flows, and Design Styles
    IEEE International Workshop on Rapid Prototyping (RSP), pp. 180-186, Geneva, Switzerland, June 2004.
    
    
39. K. Papademetriou, A. Dollas, S. Sotiropoulos
    A Real-Time Embedded I/O Device for Kinetically Challenged Persons
    XIV World Congress on Information Technology (WCIT), Athens, Greece, May 2004. Selected as outstanding work.
    
    
40. S. Sotiropoulos, K. Papademetriou, A. Dollas
    Adaptation of a Low Cost Motion Recognition System for Custom Operation from Shrink-Wrapped Hardware
    ACM SIGMM Workshop on Biometrics Methods and Applications (WBMA), pp. 107-114, Berkeley Marina Radisson CA, USA, November 2003.
    
    
41. A. Dollas, K. Papademetriou, S. Sotiropoulos, E.Sotiriades
    An Input Device to Assist Kinetically Challenged Persons Interfacing with the Environment (in Greek)
    Panhellenic Conference on Rehabilitation Medicine, pp. 82-83, Chania, Greece, October 2003.
    
    
42. K. Papademetriou, A. Dollas, S. Sotiropoulos
    A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 294-295, Napa CA, USA, April 2003.
    
    
43. A. Dollas, K. Papademetriou, N. Aslanides, T. Kean
    A Reconfigurable Embedded Input Device for Kinetically Challenged Persons
    International Conference on Field Programmable Logic and Applications (FPL), pp. 326-335, Belfast, N.Ireland, August 2001.
    
    
44. A. Dollas, D. Pnevmatikatos, N. Aslanides, S. Kavvadias, E. Sotiriades, K. Papademetriou
    Rapid Prototyping of Reusable 4x4 Active ATM Switch Core with the PCI Pamette
    IEEE International Workshop on Rapid System Prototyping (RSP), pp. 17-23, Monterey CA, USA, June 2001.
    
    
45. A. Dollas, D. Pnevmatikatos, N. Aslanides, S. Kavvadias, E. Sotiriades, S. Zogopoulos, K. Papademetriou, N. Chrysos, K. Harteros, E. Antonidakis, N. Petrakis
    Architecture and Applications of PLATO, a Reconfigurable Active Network Platform
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 101-110, Rohnert Park CA, USA, April 2001.
    
    

Patents

46. S. Sotiropoulos, A. Dollas, K. Papademetriou
    Digital Signal Processing Methods, Systems and Computer Program Products that Identify Threshold Positions and Values
    Filing date: May 20, 2005. Issue date: September 1, 2009. US Patent No. 7,583,819. Serial No. 11/133,861.
    
    

Technical Reports

47. A. Dollas, K. Papademetriou, C. Mathioudakis, E. Markatos, M. Katevenis
    Experimental ATM Network Interface Performance Evaluation
    Technical Report FORTH-ICS/TR-244, February 1999.
    
    

• October 2018 - September 2019, Neapolis University Pafos, Cyprus
  Visiting Professor
  • Computer Architecture II, taught in Greek
  • Computer Architecture I, taught in Greek and English


• May 2014 - present, Technical University of Crete, Greece
  Laboratory teaching staff
  • Logic Design (2014-17, 2019)
  • Advanced Logic Design (2016-18)
  • Digital Computers (2018)
  • Computer Organization and Design (2014-15, 2019)
  • Computer Architecture (2015)


• February 2000 - April 2014, Technical University of Crete, Greece
  Teaching assistant in the ECE department. Held review and lab sessions; lectured; held office hours; marked assignments; designed assignments
  • Logic Design (2000,2013)
  • Digital Computers (2001,2007, 2009-2012)
  • Computer Organization and Design (2000)
  • Computer Architecture (2001,2007-13)
  • Real Time Systems (2002-04)
  • Design of VLSI/ASIC Systems (2007-10)

• Top-3 cited journal's article, ACM TRETS (Transactions on Reconfigurable Technology and Systems), “Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model”, December 2011.
• Nomination for best paper award, in IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC ’13), selected amongst the 6 finalists out of 49 accepted papers (249 submitted), Istanbul, Turkey, October 7-9, 2013.
• Co-inventor of one of the first technologies developed at Technical University of Crete that got patent filing in the US, Filing date: May 20, 2005. Issue date: September 1, 2009. US Patent No. 7,583,819. Serial No. 11/133,861.
• Outstanding paper, in Michael Dertouzos Competition, event of XIV World Congress on Information Technology (WCIT ’04), selected amongst the 7 finalists out of 80 submitted papers, Athens, Greece, May 19-21, 2004.
• Outstanding diploma thesis, Ericsson Award of Excellence in Telecommunications, from ERICSSON Hellas S.A., March 6, 1998.

Review for journals
• ACM Transactions on Reconfigurable Technology and Systems (TRETS)
• ACM Transactions on Embedded Computing Systems (TECS)
• IEEE Access
• IEEE Embedded Systems Letters (ESL)
• IEEE Transactions on VLSI Systems (TVLSI)
• ELSEVIER Microelectronics Journal
• ELSEVIER Journal of Systems Architecture (JSA)
• ELSEVIER Computers and Electrical Engineering
• SPRINGER Mobile Networks and Applications (MONET)
• IET Signal Processing (IET-SPR)
• IET Computers & Digital Techniques
• IET Electronics Letters
• HINDAWI International Journal of Reconfigurable Computing (IJRC)
• International Journal of Communication Systems (IJCS)
• SPRINGER Design Automation for Embedded Systems (DAES)
• SPRINGER Journal of Signal Processing Systems

Review for conferences
• International Symposium on Applied Reconfigurable Computing (ARC)
• International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
• IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig)
• IEEE International Conference on Field Programmable Logic and Applications (FPL)
• International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN)

Served as additional reviewer (prior to Ph.D graduation)
• IEEE International Conference on Very Large Scale Integration and System-on-a-Chip (2008,2009)
• HiPEAC Workshop on Reconfigurable Computing (2008)
• IEEE International Workshop on Rapid System Prototyping (2007)
• IEEE International Conference on Field Programmable Logic and Applications (2007)
• IEEE Symposium on Field-Programmable Custom Computing Machines (2006,2007)

Member of the Editorial Advisory Board
• Handbook of Research on Heterogeneous Next Generation Networking: Innovations and Platforms (2008)

• Member of: HiPEAC (since 2012), ACM (since 2008), IEEE (since 2006)
• Languages: Greek (native), English, German (moderate)
• Service to the community:
  • Member of the Students’ Union Council of the ECE department (1993-1994, 1994-1995, 1995-1996)
  • Vice President of the Student’s Union Council of the ECE department (1992-1993)
  • Member of the Student’s Union Council of the Technical University of Crete (1992-1993)
• Hobbies: folk dancing, guitar, tennis, soccer