Partial Reconfiguration Cost Calculator (PRCC)

updated: June 13th, 2015
©2010 Kyprianos Papadimitriou
Microprocessor and Hardware Laboratory
Technical University of Crete

This formula calculates the time needed for partial reconfiguration using the internal reconfiguration port, i.e. ICAP, when controlled by the on-chip processor. It was derived based on experiments conducted on an evaluation platform. It targets Xilinx Virtex FPGAs and provides a fair estimation for different system setups using PowerPC as the reconfiguration controller. It can be used for other processors such as the Microblaze but with less accuracy. Different ways to control reconfiguration exist and certainly the incorporation of a dedicated controller offers a faster solution as compared to the on-chip processor (in WRC 2014 paper we reached a throughput of 488 MB/s). There are applications in which the reconfiguration needs to be controlled by the processor, or cases in which the researcher needs to be aware of the reconfiguration time without putting the effort or devoting resources to implement a dedicated controller. PRCC aims at supporting researchers in assessing their system and taking decisions at an early development stage prior entering the PR design flow.



Instructions to use the PRCC

After selecting the parameters of the system and entering the size of the bitstream to be reconfigured (INPUT section), the formula calculates the reconfiguration time and throughput (OUTPUT section): Currently, only the option to enter the size of the bitstream to be loaded is provided. Soon, the option to enter either the amount of configuration frames, or, the amount of resources (i.e. slices and BRAMs) that the PR module occupies, will be supported.

Experimental framework and theory used to extract the formula

The work for developing the formula is presented in the following papers. The first two papers present the experimental infrastructure for gathering the details of reconfiguration, while the third paper has the theory to obtain the formula along with its validation. In addition, the third paper has different setups to control reconfiguration, including the achieved throughput when this is done by an off-chip or on-chip processor or a dedicated controller:

Research areas that can benefit from using the formula

Reconfiguration delay varies amongst different systems as it strongly depends on the system setup itself. This formula aims to provide realistic value of the delays needed to reconfigure PR modules. It can be used for system-level evaluation by researchers considering to incorporate PR technology in their projects. Potential uses are i) pure calculation of the time needed to switch between subtasks of an application or between applications; ii) assesing whether system performance meets application requirements in accordance to the delay that can be tolerated (e.g. real-time systems); iii) extent of the performance degradation due to the reconfiguration overhead. Research fields along with some representative publications that can benefit from this work are listed below:
This page is updated occasionally. New significant entries appear with magenta color.
Suggestions for improvements are more than welcome; please send an e-mail to

Maintained by K. Papadimitriou. Special thanks to S. Karasavvidis, D. Pnevmatikatos and C. Kachris.